R is for RISC. This is the acronym for Reduced Instruction Set Computing, which seems to be the future of microprocessor design. The first PC-oriented RISC chip, the PowerPC, was released by Apple, Motorola and IBM in March 1994. But hot on its heels in the consumer market are such names as Sun Microsystems, Hewlett-Packard and even Intel, whose non-RISC chips (such as the 80x86 family and Pentium) dominate the current PC market.

Intel's designs, like those of many other microprocessors before them, use CISC - Complex Instruction Set Computing. The difference between RISC and CISC is in the way that they carry out the instructions in programs.

The best way to visualise this is as two office canteens whose aim is to push through the most customers in the shortest time. The CISC canteen offers a large range of meals, which diners browse for exactly what they want: their order is then made at high speed by backroom chefs.

The RISC canteen has a cut-down menu that is tailored to the general desires of its customers. You create your lunch from what's available at different counters: sausages, baked beans, rice, chips and so on.

In the microprocessors, these differences equate to the variety of "machine instructions" available on the chip. Older microprocessors had a huge number of available instructions (such as "take the number in storage register A, add the number in register B and put the result in register C", or "If A=B, jump to line X in this program") wired on to the chip.

But extensive research by IBM in the 1980s into patterns of computer usage found that general-purpose computers spend up to 80 per cent of their time executing simple instructions such as "load data", "store data" and "If X=Y, do Z". The more complex instructions were used infrequently. (That is, the canteen diners preferred simple fare.) The range of instructions meant the chip had to waste time picking the right sequence of processes from the alternatives.

RISC computers cut out the extraneous instructions. Any task too complex for the hardware to execute in a single cycle is done by executing a series of the basic instructions. On that basis, the RISC machine would not seem to have an advantage over the CISC design; but cutting down the instructions means the chip can be designed to carry out more instruction cycles per second. Thus RISC can compete head-on with CISC - as Apple's PowerPC range does with Pentium-based PCs - but has the option of upping the speed and the number of processes carried out in parallel, which is not available to CISC chips. Which is why it is no surprise that Intel is working with Hewlett-Packard to design RISC successors to the Pentium family.